Metal oxide semiconductor field effect transistors (MOSFETs) are transistors used in a variety of electronic devices and systems for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. MOSFETs formed on n-type or p-type semiconductor material include a channel through which current flows. The length of the channel is one of the most important parameters, which determines the performance of the MOSFET as measured by the speed of operation and the on resistance of the device. Two widely-used types of power MOSFETs are planar MOSFETs and trench MOSFETs.
FIG. 1A is a cross sectional view of a conventional planar power DMOSFET transistor. The planar DMOSFET transistor 100A includes a gate structure or stack 102A formed on a semiconductor substrate of a first conductivity type 101A, which also serves as the drain of the transistor. The gate stack 102A generally includes a thin gate dielectric layer 103A overlying the substrate 101A and a gate electrode situated over the gate dielectric layer. Source regions 104A and 105A of the first conductivity type are formed in a body region 106A of an opposite conductivity type in the substrate 101A on either side of the gate structure 102A, thereby defining a channel region 107A at the upper surface of the substrate under the gate structure. In operation, the gate electrode is biased to create an electric field to invert the channel underneath the gate dielectric layer and allowing carriers to travel through the channel between the source and drain regions.
The channel length of a planar MOSFET is typically controlled by implantation and diffusion from the edge of the gate stack. Specifically, the gate electrode on the substrate with a thin gate dielectric layer defines an edge from which implantation and diffusion are performed to form a body region. The following source implant and diffusion are also processed from the same gate electrode edge. The channel length is determined according to implant energy and thermal cycles of the body and source diffusions. It thus provides a tighter process control and ease of manufacturing.
In the planar power MOSFET structure as shown in FIG. 1A, the carriers from the source have to pass through a region between the two body regions before they reaches the drain region (101A). The depletion regions between the bodies and the drain reduce the conductance of the current path thus increase the on-resistance of the device. It is due to this JFET effect that limits the scaling for the planar power MOSFET.
Compared to planar power MOSFETs, trench power MOSFETs have higher cell density. FIG. 1B is a cross sectional view showing a conventional trench MOSFET. The trench MOSFET 100B includes a plurality of trenches 102B formed in a substrate 101B, which also serves as the drain region of the transistor. The vertical sidewalls and the bottom of the trenches are lined with a layer of gate insulation 103B. Each trench 102B is at least partially filled with electrically conductive gate electrode material 108B, such as doped polysilicon. The trench MOSFET 100B also includes a body region of the second conductivity type 106B formed in the substrate 101B, and source region 105B formed above the body region 106B. A drain contact 104B is provided at the bottom of the substrate. Upon application of a voltage above the threshold voltage to gate conductive material 108B, a portion of body region 106B adjacent the gate insulation 103B is inverted to form a channel region 107B which allows a source region adjacent the channel region to be electrically connected to the drain below the body region 106B. The channel length control is typically from the surface of the mesa. Specifically, after formation of the trenches, the body region is formed by implanting into the mesa followed by diffusion. This process is repeated for forming the source region. The channel length is determined by the difference between the body region and source region referenced to the surface of the mesa.
The gate length of the trench MOSFET structure is determined by the difference in trench depth and the recess of the gate conductive material in the trench. If the recessed portion is too deep, it would have weak overlap between the gate electrode and source region. In addition, the body region can pinch off at the bottom of the trench when the trench is shallower in depth comparable to the body region. As a result, it would have a weak overlap between the gate and drain and as well as a higher Rdson (i.e., On-resistance). To avoid the above issues, a deep source region and a deep trench are required. A deep source region requires a deeper body region. However, it would be difficult to have a short channel length with a deep body and source regions.
Thus, there is a need for providing a trench MOSFET with a controllable short channel length. It is within this context that aspects of the present disclosure arise.